Add support for Cortex-A57 erratum 826974 workaround

Change-Id: I45641551474f4c58c638aff8c42c0ab9a8ec78b4

diff --git a/docs/cpu-specific-build-macros.md b/docs/cpu-specific-build-macros.md
index c57dc7ee54be84804c919d2268dd923c913338e4..408af36bfe7ba509b14984e80f9d1bc8a51d131a 100644 (file)
--- a/docs/cpu-specific-build-macros.md
+++ b/docs/cpu-specific-build-macros.md
@@ -60,6 +60,9 @@ For Cortex-A57, following errata build flags are defined :
 *   `ERRATA_A57_813420`: This applies errata 813420 workaround to Cortex-A57
      CPU. This needs to be enabled only for revision r0p0 of the CPU.
 
+*   `ERRATA_A57_826974`: This applies errata 826974 workaround to Cortex-A57
+     CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+
 3.  CPU Specific optimizations
 ------------------------------
 

diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h
index c512129a17d0c3bb886737c2c972c5a73ed4459d..7711e690aac49c75e7248bd55ae5525793f5f925 100644 (file)
--- a/include/lib/cpus/aarch64/cortex_a57.h
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -61,6 +61,7 @@
  ******************************************************************************/
 #define CPUACTLR_EL1                   S3_1_C15_C2_0   /* Instruction def. */
 
+#define CPUACTLR_DIS_LOAD_PASS_DMB     (1 << 59)
 #define CPUACTLR_DIS_OVERREAD          (1 << 52)
 #define CPUACTLR_NO_ALLOC_WBWA         (1 << 49)
 #define CPUACTLR_DCC_AS_DCCI           (1 << 44)

diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index 4c0b8ce3813780f70b8b2db9e56df72cd9ee8677..d992f98b7230054f5c9e8dfce49f9b5619091474 100644 (file)
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -167,6 +167,33 @@ disable_hint:
        ret
 endfunc a57_disable_ldnp_overread
 
+       /* ---------------------------------------------------
+        * Errata Workaround for Cortex A57 Errata #826974.
+        * This applies only to revision <= r1p1 of Cortex A57.
+        * Inputs:
+        * x0: variant[4:7] and revision[0:3] of current cpu.
+        * Clobbers : x0 - x5
+        * ---------------------------------------------------
+        */
+func errata_a57_826974_wa
+       /*
+        * Compare x0 against revision r1p1
+        */
+       cmp     x0, #0x11
+       b.ls    apply_826974
+#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
+       b       print_revision_warning
+#else
+       ret
+#endif
+apply_826974:
+       mrs     x1, CPUACTLR_EL1
+       orr     x1, x1, #CPUACTLR_DIS_LOAD_PASS_DMB
+       msr     CPUACTLR_EL1, x1
+       ret
+endfunc errata_a57_826974_wa
+
+
        /* -------------------------------------------------
         * The CPU Ops reset function for Cortex-A57.
         * Clobbers: x0-x5, x15, x19, x30
@@ -200,6 +227,11 @@ func cortex_a57_reset_func
        bl      a57_disable_ldnp_overread
 #endif
 
+#if ERRATA_A57_826974
+       mov     x0, x15
+       bl      errata_a57_826974_wa
+#endif
+
        /* ---------------------------------------------
         * Enable the SMP bit.
         * ---------------------------------------------

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 1ed7d140f34a70ff1f0efbcb3783c44d254f8aa3..3ea462bb6205ed750500604535802f5c075bdcfc 100644 (file)
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -74,6 +74,10 @@ ERRATA_A57_806969    ?=0
 # only to revision r0p0 of the Cortex A57 cpu.
 ERRATA_A57_813420      ?=0
 
+# Flag to apply erratum 826974 workaround during reset. This erratum applies
+# only to revision <= r1p1 of the Cortex A57 cpu.
+ERRATA_A57_826974      ?=0
+
 # Process ERRATA_A53_826319 flag
 $(eval $(call assert_boolean,ERRATA_A53_826319))
 $(eval $(call add_define,ERRATA_A53_826319))
@@ -89,3 +93,7 @@ $(eval $(call add_define,ERRATA_A57_806969))
 # Process ERRATA_A57_813420 flag
 $(eval $(call assert_boolean,ERRATA_A57_813420))
 $(eval $(call add_define,ERRATA_A57_813420))
+
+# Process ERRATA_A57_826974 flag
+$(eval $(call assert_boolean,ERRATA_A57_826974))
+$(eval $(call add_define,ERRATA_A57_826974))